The present invention relates to a method for manufacturing a semiconductor device having a through via structure.
The die size of semiconductor devices has become smaller. Further, an integrated circuit may have a three-dimensional structure formed by stacking the chips of a semiconductor device. In this case, a structure extending through a silicon substrate, or through silicon via (TSV), is used. The TSV technology allows for stacking of semiconductor devices within a package and couples the semiconductor devices on the top and bottom surfaces. That is, this technology couples chips within a minimum distance, which allows for further sophisticated functions and higher operational speeds.
Japanese Laid-Open Patent Publication No. 2007-251145 (page 1 and FIG. 2) describes one example of a layered package that uses TSV technology. The layered package described in the publication includes a first wire coupled to a bonding pad on a top surface of the layered package, a through silicon via extending through the layered package and coupled to the first wire, and a second wire coupled to the through silicon via on a bottom surface of the layered package. Semiconductor chips are coupled by solder balls.
A process for manufacturing such a TSV structure will now be discussed with reference to FIGS. 5 and 6.
First, referring to FIG. 5A, via holes 101 are formed in predetermined regions of a silicon substrate 10.
Then, as shown in FIG. 5B, an oxide layer 12 is formed on the side walls and bottom walls of each via hole 101. More specifically, the silicon substrate 10 is oxidized to form an oxide film on its surface. Then, a conductive layer 102 is formed on the oxide layer 12 of each via hole 101. In this case, low-pressure chemical vapor deposition (CVD) is performed to deposit a polycrystalline silicon film on the oxide film formed on the silicon substrate 10. Then, the surface of the silicon substrate 10 is etched leaving the oxide film and polycrystalline silicon in each via hole 101. This forms a trench structure including the oxide layer 12 and the conductive layer 102.
Referring to FIG. 5C, a desired device 11 and insulation layers 13 are then formed on the silicon substrate 10 between the via holes 101. The insulation layers 13 are formed to insulate a wiring layer on a chip from the silicon substrate 10. Contact holes are formed in the insulation layers 13, which are arranged on the conductive layers 102.
Referring to FIG. 5D, wiring layers 14 are then formed to couple the device 11 and the conductive layers 102. The wiring layers 14 are coupled to the conductive layers 102 through the contact holes.
Referring to FIG. 5E, a protective layer 15 is then formed on the device 11 and the wiring layers 14. The protective layer 15 is formed to protect the device 11 and the wiring layer 14 in subsequent processes. Phosphosilicate glass (PSG), which is formed through CVD, may be used as the protective layer 15.
Referring to FIG. 6A, the silicon substrate 10 is then ground and polished from the bottom surface. Chemical-mechanical polishing (CMP) may be performed to grind and polish the silicon substrate 10. In this case, the polishing is performed until the conductive layers 102 buried in the via holes 101 are exposed.
Referring to FIG. 6B, an insulation layer 16 is then formed on the bottom side of the silicon substrate 10. Since the device 11 and the wiring layers 14 are formed on the top side of the silicon substrate 10, the insulation layer 16 must be formed through a process that is performed at a relatively low temperature. For example, low-temperature CVD may be performed to form the insulation layer 16.
Referring to FIG. 6C, contact holes 161 are formed in the insulation layer 16 in connection with the conductive layers 102.
Referring to FIG. 6D, electrodes 17, which are coupled to the conductive layers 102 through the contact holes 161, are then formed. As a result, the electrodes 17, which are for the device 11 formed on the top surface of the silicon substrate 10, are formed on the bottom side of the silicon substrate 10.
U.S. Patent Application Publication No. 2007/0164443 (page 1 and FIG. 8) describes one example of a method for manufacturing a semiconductor device using a silicon on insulator (SOI) substrate in which a semiconductor layer is applied to a semiconductor substrate with an insulation layer arranged in between. The method described in the publication forms a device on a top surface of the substrate, forms a through hole in a buried oxide film, and couples the device to a bottom surface of the substrate.
In the prior art, however, when reducing the thickness of the layers on a silicon substrate, it is difficult to control the thickness. Further, the insulation layer formed on the bottom surface of the silicon substrate 10 must be formed using a low-temperature process so that the semiconductor devices and wiring layers are not affected. It is thus difficult to form a high quality insulation layer.